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    NANO-NET

    1st International ICST Conference on Nano-Networks

    The Nano-Net conference positions itself at the intersection of two worlds, namely, emerging nanotechnologies on one-side, and network/communication theory on the other side. The standing question that this conference will address is: What are the new communication paradigms that derive from the tr…

    The Nano-Net conference positions itself at the intersection of two worlds, namely, emerging nanotechnologies on one-side, and network/communication theory on the other side. The standing question that this conference will address is: What are the new communication paradigms that derive from the transition from micro- to nano-scale devices? The related degrees of freedom and constraints associated with these new technologies will change our notions about efficient network and system design. Nano-Net provides a multidisciplinary forum for the discussion of new techniques in modeling, design, simulation, and fabrication of network and communication systems at the nano-scale.

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    Editor(s): Gian Mario Maggio (STMicroelectronics, Switzerland) and Chris Dwyer (Duke University, USA )
    Publisher
    IEEE
    ISBN
    1-4244-0391-X
    Conference dates
    14th–16th Sep 2006
    Location
    Lausanne, Switzerland
    Appeared in EUDL
    2011-11-29

    Copyright © 2011–2025 IEEE

    Ordered by title or year
    Showing 1–10 of 28 results
    Page size: 102550
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    • 3D Nanowire-Based Programmable Logic

      Research Article in 1st International ICST Conference on Nano-Networks

      B. Gojman, R. Rubin, C. Pilotto, A. DeHon, T. Tanamoto
    • 3D on-chip networking technology based on post-silicon devices for future networks-on-chip

      Research Article in 1st International ICST Conference on Nano-Networks

      S. Fujita, K. Nomura, K. Abe, T.H. Lee
    • A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects

      Research Article in 1st International ICST Conference on Nano-Networks

      Park Dongkook , C. Nicopoulos, Jongman Kim, N. Vijaykrishnan, C.R. Das
    • A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

      Research Article in 1st International ICST Conference on Nano-Networks

      I. Miro Panades, A. Sheibanyrad, A. Greiner
    • A Theoretical Framework for On-chip Stochastic Communication Analysis

      Research Article in 1st International ICST Conference on Nano-Networks

      P. Bogdan, R. Marculescu
    • Area and Power Modeling Methodologies for Networks-on-Chip

      Research Article in 1st International ICST Conference on Nano-Networks

      P. Melonit, S. Carta, R. Argiolas, L. Raffo, F. Angiolini
    • Can Carbon Nanotubes Extend the Lifetime of On-Chip Electrical Interconnections?

      Research Article in 1st International ICST Conference on Nano-Networks

      K. Banerjee, N. Srivastava, S. Im
    • Connecting and Configuring Defective Nano-Scale Networks for DNA Self-Assembly

      Research Article in 1st International ICST Conference on Nano-Networks

      L. Demoracski, F. Lombardi
    • Controlled nanowire fabrication by PEDAL process

      Research Article in 1st International ICST Conference on Nano-Networks

      S. Sonkusale, P. Franzon
    • Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices

      Research Article in 1st International ICST Conference on Nano-Networks

      A. Venkataratnam, A.K. Goel
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