Controlled nanowire fabrication by PEDAL process

In earlier publications, the authors proposed and successfully demonstrated an unconventional lithographic technique called PEDAL process (planar edge defined alternate layer) to define wafer scale sub 25 nm nanowires and nanoimprint template. In this publication, uniformity analysis of the width and spacing of an array of sixteen line-width structures with approximately 42 nm pitch and twenty four line-width structures with approximately 23 nm pitch, fabricated by PEDAL process, is presented. Results on routing capability of this process along with results of palladium nanowires obtained by PEDAL lift-off process done on the template with 42 nm pitch is also reported. In the case of template with array of sixteen lines, the average pitch of array across the 4 inch wafer was measured to be 40.83 nm with the standard deviation of 2.29 nm where as the average pitch of the lines in an array was found to be 41.5 nm with the standard deviation of 4.64 nm. After Pd liftoff the average pitch in nanowire array was measured to be 41.88 nm with standard deviation of 1.83 nm, close to the values obtained for the template. In the case of array of twenty four line-widths, average pitch of array across the 4 inch wafer was measured to be 21.1 nm with the standard deviation of 5 A where as the average pitch of the line in an array was found to be 22.6 nm with the standard deviation of 9 A. The experimental results presented in this paper prove the efficacy of PEDAL process in making nanowire template of sub-25 nm wide lines with good routing capability