inis 23(1): e3

Research Article

Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA

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  • @ARTICLE{10.4108/eetinis.v10i1.2630,
        author={Minh Thuong Nguyen and Xuan Nam Tran and Vu Duc Ngo and Quang-Kien Trinh and Duc Thang Nguyen and Tien Anh Vu},
        title={Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA},
        journal={EAI Endorsed Transactions on Industrial Networks and Intelligent Systems},
        volume={10},
        number={1},
        publisher={EAI},
        journal_a={INIS},
        year={2023},
        month={3},
        keywords={SDM-MIMO, Sphere Detection, K-best, MIMO, FPGA, Sub-Optimal, Wireless communication},
        doi={10.4108/eetinis.v10i1.2630}
    }
    
  • Minh Thuong Nguyen
    Xuan Nam Tran
    Vu Duc Ngo
    Quang-Kien Trinh
    Duc Thang Nguyen
    Tien Anh Vu
    Year: 2023
    Sub-optimal Deep Pipelined Implementation of MIMO Sphere Detector on FPGA
    INIS
    EAI
    DOI: 10.4108/eetinis.v10i1.2630
Minh Thuong Nguyen1, Xuan Nam Tran2, Vu Duc Ngo3, Quang-Kien Trinh2,*, Duc Thang Nguyen2, Tien Anh Vu2
  • 1: Military Information Technology Institute, Hanoi, Vietnam
  • 2: Le Quy Don Technical University
  • 3: Hanoi University of Science and Technology
*Contact email: kien.trinh@lqdtu.edu.vn

Abstract

Sphere detector (SD) is an effective signal detection approach for the wireless multiple-input multiple-output (MIMO) system since it can achieve near-optimal performance while reducing significant computational complexity. In this work, we proposed a novel SD architecture that is suitable for implementation on the hardware accelerator. We first perform a statistical analysis to examine the distribution of valid paths in the SD search tree. Using the analysis result, we then proposed an enhanced hybrid SD (EHSD) architecture that achieves quasi-ML performance and high throughput with a reasonable cost in hardware. The fine-grained pipeline designs of 4 × 4 and 8 × 8 MIMO system with 16-QAM modulation delivers throughput of 7.04 Gbps and 14.08 Gbps on the Xilinx Virtex Ultrascale+ FPGA, respectively.