Research Article
Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time
@ARTICLE{10.4108/eai.27-6-2018.155236, author={Minh Huan Vo}, title={Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time}, journal={EAI Endorsed Transactions on Industrial Networks and Intelligent Systems}, volume={5}, number={15}, publisher={EAI}, journal_a={INIS}, year={2018}, month={8}, keywords={low-leakage, power gating, sleep transistor, fine-grain leakage control, crossover time, wake-up time}, doi={10.4108/eai.27-6-2018.155236} }- Minh Huan Vo
Year: 2018
Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time
INIS
EAI
DOI: 10.4108/eai.27-6-2018.155236
Abstract
The power gating is one of the most popular reduction leakage techniques. We make comparison among various power gating schemes in terms of power delay product, energy loss, and wake-up time using the 45-nm Predictive Technology Model. In my conclusion, the Dual-Switch Power Gating (DSPG) shows lower power delay product, smaller energy loss, faster wake-up time than the other power gating schemes such as the Single-Switch and Charge-Recycled Power Gating schemes. Based on these advantages, the DSPG is suggested in this paper as a viable candidate suitable to a fine-grain leakage control scheme, where logic blocks go in and out very frequently and shortly between the active and sleep modes.
Copyright © 2018 Huan Minh Vo, licensed to EAI. This is an open access article distributed under the terms of the Creative Commons Attribution license (http://creativecommons.org/licenses/by/3.0/), which permits unlimited use, distribution and reproduction in any medium so long as the original work is properly cited.
