Research Article
All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs
@ARTICLE{10.4108/eai.24-10-2019.160983, author={Van-Thanh Ta and Van-Phuc Hoang and Xuan Nam Tran}, title={All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs}, journal={EAI Endorsed Transactions on Industrial Networks and Intelligent Systems}, volume={6}, number={21}, publisher={EAI}, journal_a={INIS}, year={2019}, month={10}, keywords={Time-interleaved analog-to-digital converter, channel mismatches, all-digital background calibration}, doi={10.4108/eai.24-10-2019.160983} }- Van-Thanh Ta
Van-Phuc Hoang
Xuan Nam Tran
Year: 2019
All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs
INIS
EAI
DOI: 10.4108/eai.24-10-2019.160983
Abstract
This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs). The averaging technique is used to remove the offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the subADC over the reference ADC. Timing skew is compensated by using Hadamard transform for error correction and least mean squares (LMS) algorithm for estimation of the clock skew. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations.
Copyright © 2019 Van-Thanh Ta et al., licensed to EAI. This is an open access article distributed under the terms of the Creative Commons Attribution licence (http://creativecommons.org/licenses/by/3.0/), which permits unlimited use, distribution and reproduction in any medium so long as the original work is properly cited.