inis 19(21): e3

Research Article

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

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  • @ARTICLE{10.4108/eai.24-10-2019.160983,
        author={Van-Thanh  Ta and Van-Phuc  Hoang and Xuan  Nam  Tran},
        title={All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs},
        journal={EAI Endorsed Transactions on Industrial Networks and Intelligent Systems},
        volume={6},
        number={21},
        publisher={EAI},
        journal_a={INIS},
        year={2019},
        month={10},
        keywords={Time-interleaved analog-to-digital converter, channel mismatches, all-digital background calibration},
        doi={10.4108/eai.24-10-2019.160983}
    }
    
  • Van-Thanh Ta
    Van-Phuc Hoang
    Xuan Nam Tran
    Year: 2019
    All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs
    INIS
    EAI
    DOI: 10.4108/eai.24-10-2019.160983
Van-Thanh Ta1,*, Van-Phuc Hoang1, Xuan Nam Tran1
  • 1: Le Quy Don Technical University, Hanoi, Vietnam
*Contact email: tvthanh@tcu.edu.vn

Abstract

This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs). The averaging technique is used to remove the offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the subADC over the reference ADC. Timing skew is compensated by using Hadamard transform for error correction and least mean squares (LMS) algorithm for estimation of the clock skew. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations.