2nd International ICST Conference on Simulation Tools and Techniques

Research Article

Cache simulator based on GPU acceleration

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        author={Wan  Han and Gao  Xiaopeng and Wang  Zhiqiang},
        title={Cache simulator based on GPU acceleration},
        proceedings={2nd International ICST Conference on Simulation Tools and Techniques},
        keywords={Multi-core GPGPU Trace-driven Cache Simulator CUDA},
  • Wan Han
    Gao Xiaopeng
    Wang Zhiqiang
    Year: 2010
    Cache simulator based on GPU acceleration
    DOI: 10.4108/ICST.SIMUTOOLS2009.5562
Wan Han1,*, Gao Xiaopeng1,*, Wang Zhiqiang1,*
  • 1: School of Computer Science and Engineering, Beijing University of Aeronautics & Astronautics. +86-010-82338059
*Contact email: wanhan@cse.buaa.edu.cn, gxp@buaa.edu.cn, wangzhiqiang@buaa.edu.cn


Cache technology plays a fundamental role in modern computer systems as it serves the purpose of matching the speed gap between processor and memory. Trace-driven simulator has been widely adopted in the process of design and evaluation of cache architectures. However, as the cache design moves to more complicated architectures, size of the trace is becoming larger and larger. Traditional simulation methods, which can only execute simulation operations in sequence, are no longer practical due to their long simulation cycles. In this paper, we explore both set-parallelism and search-parallelism in cache simulation process, and map our parallel algorithm to GPU-CPU platform. And we propose a trace-driven cache simulator on GPU using Compute Unified Device Architecture (CUDA). Our experimental result shows that the new algorithm gains 2.5x performance improvement compared to traditional CPU-based serial algorithm.