Research Article
Improving Processor Hardware Compiled Cycle Accurate Simulation using Program Abstraction
@INPROCEEDINGS{10.4108/icst.simutools.2014.254792, author={Jean-Luc B\^{e}chennec and Adrien Bullich and Mika\`{\i}l Briday and Yvon Trinquet}, title={Improving Processor Hardware Compiled Cycle Accurate Simulation using Program Abstraction}, proceedings={Seventh International Conference on Simulation Tools and Techniques}, publisher={ICST}, proceedings_a={SIMUTOOLS}, year={2014}, month={8}, keywords={processor hardware simulation; compiled simulation; cycle accurate simulation; real-time systems}, doi={10.4108/icst.simutools.2014.254792} }- Jean-Luc Béchennec
Adrien Bullich
Mikaël Briday
Yvon Trinquet
Year: 2014
Improving Processor Hardware Compiled Cycle Accurate Simulation using Program Abstraction
SIMUTOOLS
ICST
DOI: 10.4108/icst.simutools.2014.254792
Abstract
Verification is an important step in the development of real-time embedded systems. The validation of a real-time system uses a timing accurate simulator and, when the actual binary code is used, a cycle accurate simulator (CAS). However, a CAS is slow especially when the simulated processor is complex and the application is big. One way to improve the speed of a CAS is to use compiled simulation. In this scheme, the application binary code model is merged with the processor model. This allows to remove operations from the simulator and to speed up it. In this paper, we show how to use an abstraction of the program and improve the handling of functions calls. The resulted simulator is temporally and functionally equivalent. This technique improves simulation speed by more than 50% over the speed of an interpreted CAS.