Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation

Masoud Oveis-Gharan; Gul Khan

Seventh International Conference on Simulation Tools and Techniques

Research Article

Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation

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Cite: BibTeX Plain Text

@INPROCEEDINGS{10.4108/icst.simutools.2014.254626,
    author={Masoud Oveis-Gharan and Gul Khan},
    title={Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation},
    proceedings={Seventh International Conference on Simulation Tools and Techniques},
    publisher={ICST},
    proceedings_a={SIMUTOOLS},
    year={2014},
    month={8},
    keywords={network-on-chip systemc based modeling system-on-chip design},
    doi={10.4108/icst.simutools.2014.254626}
}

Masoud Oveis-Gharan
Gul Khan
Year: 2014
Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation
SIMUTOOLS
ICST
DOI: 10.4108/icst.simutools.2014.254626

Masoud Oveis-Gharan¹, Gul Khan¹^,*

1: Ryerson University

*Contact email: gnkhan@ee.ryerson.ca

Abstract

In this paper, a Flexible And Accurate Network-On-chip Simulator (FAANOS) is introduced. NoC is a critical structure for system-on-chip design. We discuss the structure of its various components by presenting their details. We also provide an analytical methodology that employs the micro-architectural level of routers and links of NoC by considering their power and chip area requirements. We go through the structure of FAANOS when it is in switching mode and explain the transactional power estimation metric. To evaluate the effectiveness of an NoC system, an evaluation flow for early stage design and simulation of NoC is presented.

Keywords: network-on-chip systemc based modeling system-on-chip design

Published: 2014-08-18
Publisher: ICST

: http://dx.doi.org/10.4108/icst.simutools.2014.254626