2nd Internationa ICST Conference on Nano-Networks

Research Article

Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support

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  • @INPROCEEDINGS{10.4108/ICST.NANONET2007.2148,
        author={Kristina Kunert and Mattias Weckst\^{e}n and Magnus Jonsson},
        title={Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support},
        proceedings={2nd Internationa ICST Conference on Nano-Networks},
        proceedings_a={NANO-NET},
        year={2010},
        month={5},
        keywords={Network-on-Chip topology design feasibility analysis real-time communication reconfigurable systems.},
        doi={10.4108/ICST.NANONET2007.2148}
    }
    
  • Kristina Kunert
    Mattias Weckstén
    Magnus Jonsson
    Year: 2010
    Algorithm for the Choice of Topology in Reconfigurable On-Chip Networks with Real-Time Support
    NANO-NET
    ICST
    DOI: 10.4108/ICST.NANONET2007.2148
Kristina Kunert1,*, Mattias Weckstén1,*, Magnus Jonsson1,*
  • 1: Centre for Research on Embedded Systems (CERES), Halmstad University, Sweden
*Contact email: kristina.kunert@ide.hh.se, mattias.wecksten@ide.hh.se, magnus.jonsson@ide.hh.se

Abstract

Many future embedded systems are likely to contain System-on-Chip solutions with on-chip networks and in order to achieve high aggregated throughputs in these networks, a switched topology can be used. For further performance improvements, the topology can be adapted to application demands, either when designing the chip or by run-time reconfiguration between different predefined application modes. In this paper, we present an algorithm for the choice of topology in, e.g., on-chip networks, considering realtime demands in terms of throughput and delay often put on such systems. To further address possible real-time demands, we include a feasibility analysis to check that the application, when mapped onto the system, will behave in line with its real-time demands. With input information about traffic characteristics, our algorithm creates a topology and generates routing information for all logical traffic channels. In a case study, we show that our algorithm results in a topology that can outperform the use of state of the art topologies for high-performance computer architectures.