2nd Internationa ICST Conference on Nano-Networks

Research Article

Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder

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  • @INPROCEEDINGS{10.4108/ICST.NANONET2007.2029,
        author={Helia Naeimi and Andre DeHon},
        title={Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder},
        proceedings={2nd Internationa ICST Conference on Nano-Networks},
        proceedings_a={NANO-NET},
        year={2010},
        month={5},
        keywords={},
        doi={10.4108/ICST.NANONET2007.2029}
    }
    
  • Helia Naeimi
    Andre DeHon
    Year: 2010
    Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder
    NANO-NET
    ICST
    DOI: 10.4108/ICST.NANONET2007.2029
Helia Naeimi1,*, Andre DeHon2,*
  • 1: Computer Science California Institute of Technology Mail Stop: 256-80 Pasadena, CA 91125
  • 2: Electrical and System Engineering University of Pennsylvania Philadelphia, PA 19104
*Contact email: helia@caltech.edu, andre@acm.org

Abstract

We introduce a nanowire-based, sublithographic memory architecture tolerant to transient faults. Both the storage elements and the supporting ECC encoder and corrector are implemented in dense, but potentially unreliable, nanowire-based technology. This compactness is made possible by a recently introduced Fault-Secure detector design [18]. Using Euclidean Geometry error-correcting codes (ECC), we identify particular codes which correct up to 8 errors in data words, achieving a FIT rate at or below one for the entire memory system for bit and nanowire transient failure rates as high as 10-17 upsets/device/cycle with a total area below 1.7 x the area of the unprotected memory for memories as small as 0.1 Gbit. We explore scrubbing designs and show the overhead for serial error correction and periodic data scrubbing can be below 0.02% for fault rates as high as 10-20 upsets/device/cycle. We also present a design to unify the error-correction coding and circuitry used for permanent defect and transient fault tolerance.