Research Article
ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit
@ARTICLE{10.4108/ew.6035, author={Kannan Nithin K.V. and Balaji V.R. and Mani V. and V. Priya and S.S. Sivaraju and Duraivel A.N.}, title={ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit}, journal={EAI Endorsed Transactions on Energy Web}, volume={11}, number={1}, publisher={EAI}, journal_a={EW}, year={2024}, month={12}, keywords={ALU, CMOS, Energy Efficient, VLSI, Arithmetic}, doi={10.4108/ew.6035} }- Kannan Nithin K.V.
Balaji V.R.
Mani V.
V. Priya
S.S. Sivaraju
Duraivel A.N.
Year: 2024
ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit
EW
EAI
DOI: 10.4108/ew.6035
Abstract
Low power techniques are becoming more important as portable digital applications expand quickly and demand high speed and low power consumption. The ALU is the most crucial and essential component of a central processing unit, as well as numerous embedded systems and microprocessors. Designing a 32-bit ALU that combines an arithmetic unit and a logical unit is the task at hand. The logic unit will do logic operations AND, OR, XOR, and XNOR with the aid of the recommended CMOS technology, while the arithmetic unit will do the arithmetic operations addition, subtraction, increment, and buffering operation. The arithmetic unit is constructed using the 4x1 MUX, 2x1 MUX, and full adder, and the 4x1 MUX, required logic gates, and 4x1 MUX are employed to create the logical unit. Using Cadence Virtuoso Gpdk 180nm Technology, the results of the simulation of the 32-bit ALU, the ideal delay, and the Power were calculated.
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