TC-LEG: Topology-Constrained Sequential Energy Management in Digital-Twin Smart Grids

INTRODUCTION: The increasing integration of renewable energy, distributed storage, and flexible loads has introduced substantial uncertainty and operational complexity into modern smart grids. Existing energy management methods can optimize multi-period dispatch or encode the physical grid topology, but they often do not explicitly represent the execution order and conditional dependencies among heterogeneous control actions. OBJECTIVES: This paper aims to develop a safe and energy-efficient sequential control generation framework for digital-twin smart grids that reduces operating cost and renewable curtailment while maintaining voltage security and action feasibility. METHODS: A topology-constrained latent execution graph learning framework, termed TC-LEG, is proposed. TC-LEG uses a physical grid graph to encode electrical connectivity and operating states, while a distinct latent execution graph represents state-dependent dependencies among storage dispatch, renewable curtailment, demand response, reactive compensation, and topology switching. A hybrid discrete–continuous control sequence generator produces multi-step actions, and a simulation-oriented digital twin synchronizes the current grid state, verifies each candidate action, projects infeasible actions onto a state-dependent feasible set, and feeds the accepted action and updated state back to subsequent generation steps. RESULTS: On the IEEE 33-bus system, TC-LEG achieves a normalized operating cost of 0.811, a voltage violation rate of 0.9%, a renewable curtailment rate of 4.9%, and an action feasibility rate of 98.5%. Its average inference time is 18.6 ms on the IEEE 33-bus system and 28.4 ms on the IEEE 69-bus system, both substantially shorter than the 15-minute control interval. CONCLUSION: TC-LEG provides a topology-aware and interpretable approach to sequential energy management by combining electrical-topology representation, action-dependency learning, hybrid control generation, and digital-twin verification in a closed-loop inference process.