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Editorial

Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations

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  • @ARTICLE{10.4108/eetsis.5004,
        author={S Usha and M Kanthimathi},
        title={Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations},
        journal={EAI Endorsed Transactions on Scalable Information Systems},
        volume={11},
        number={3},
        publisher={EAI},
        journal_a={SIS},
        year={2024},
        month={2},
        keywords={PPA, Three-Operand Adder, Modular Arithmetic, FPGA},
        doi={10.4108/eetsis.5004}
    }
    
  • S Usha
    M Kanthimathi
    Year: 2024
    Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations
    SIS
    EAI
    DOI: 10.4108/eetsis.5004
S Usha1,*, M Kanthimathi1
  • 1: Sri Sairam Engineering College
*Contact email: usha.ece@sairam.edu.in

Abstract

Binary Three-operand adder serves as a foundation block used within security and Pseudo Random-Bit Generator (PRBG) systems. Binary Three-operand adder was designed using Carry Save Adder but this consumes more delay.  Therefore, a Parallel Prefix Adder (PPA) method can be utilized for faster operation. The canonical types of PPA result in a lesser path delay of approximately   O (log2 n). These adders can be designed for 8, 16, 24 or n bits. But this work is focused on developing a 24-bit three-operand adder that takes three 24-bit binary numbers as input and generates a 24-bit sum output and a carry using five different PPA methods The proposed summing circuits are operationalized with Hardware-Description-Language (HDL) using Verilog, and then subjected to synthesis using Field -Programmable Gate- Array (FPGA) Vertex 5. On comparing the proposed adders, it shows that the delay and the size occupied are significantly less in the Sklansky PPA. These faster three-operand adders can be utilized for three-operand multiplication in image processing applications and Internet of Things (IoT) security systems.

Keywords
PPA, Three-Operand Adder, Modular Arithmetic, FPGA
Received
2023-11-11
Accepted
2024-01-23
Published
2024-02-01
Publisher
EAI
http://dx.doi.org/10.4108/eetsis.5004

Copyright © 2024 S. Usha et al., licensed to EAI. This is an open access article distributed under the terms of the CC BY-NC-SA 4.0, which permits copying, redistributing, remixing, transformation, and building upon the material in any medium so long as the original work is properly cited.

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