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IoT 24(1):

Research Article

FPGA implementation of sobel edge detection algorithm

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  • @ARTICLE{10.4108/eetiot.5148,
        author={K.  Navinkumar and R. Logesh and P. VishnuBabu and Ananthalakshmi A.V.},
        title={FPGA implementation of sobel edge detection algorithm},
        journal={EAI Endorsed Transactions on Internet of Things},
        volume={10},
        number={1},
        publisher={EAI},
        journal_a={IOT},
        year={2024},
        month={12},
        keywords={Sobel edge detection algorithm, Matlab, FPGA},
        doi={10.4108/eetiot.5148}
    }
    
  • K. Navinkumar
    R. Logesh
    P. VishnuBabu
    Ananthalakshmi A.V.
    Year: 2024
    FPGA implementation of sobel edge detection algorithm
    IOT
    EAI
    DOI: 10.4108/eetiot.5148
K. Navinkumar1, R. Logesh1, P. VishnuBabu1, Ananthalakshmi A.V.1,*
  • 1: Puducherry Technological University
*Contact email: anantha_av@ptuniv.edu.in

Abstract

Sobel Edge detection algorithm is used to extract the edges (region of maximum variation) from an image. It is based on the concept that the edges of an image contains maximum information whose computation depends on multipliers and square root. As multipliers consume more logic, a modified sobel edge detection algorithm which does not employ multipliers and square root function is proposed. A mathematical model of the proposed sobel edge algorithm was first developed and MATLAB was used to verify the model. On comparing with the original model, the proposed model has a SSIM of 96.43%. To analyse the hardware complexity, Verilog model of the modified sobel edge detection algorithm was developed using Quartus II. The chosen evaluation board is Cylone III FPGA EP3C120F780. The performance metrics such has Logic Elements utilization, Power dissipation and Maximum Operating Frequency were obtained. Open-Source toolchain (Yosys, OpenVPR, and Google Skywater 130nm PDK) was used to obtain the RTL Netlist and Synthesis reports. Verilog Modules for the Camera (CMOS OV7670) interface and FIFO Buffer were synthesized. The modified algorithm was integrated with them. An HSMC (HSMB) breakout board was connected to the FPGA Development board to increase the number of I/O ports. Thus in real time, the proposed modified Sobel Edge detection system can be used as a pre-processor to reduce the amount of computations and power consumption.

Keywords
Sobel edge detection algorithm, Matlab, FPGA
Received
2024-12-05
Accepted
2024-12-05
Published
2024-12-05
Publisher
EAI
http://dx.doi.org/10.4108/eetiot.5148

Copyright © 2024 Navinkumar et al., licensed to EAI. This is an open access article distributed under the terms of the CC BY-NCSA 4.0, which permits copying, redistributing, remixing, transformation, and building upon the material in any medium so long as the original work is properly cited.

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