Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bharath University, Chennai, India

Research Article

Design of SOC Based SRAM Cluster for Reliability and Functional Safety Applications

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  • @INPROCEEDINGS{10.4108/eai.7-6-2021.2308775,
        author={Dr.A.  Ranganayakulu and Dr.V. Surya Narayana and Dr.M.V. Nageswara Rao},
        title={Design of SOC Based SRAM Cluster for Reliability and Functional Safety Applications},
        proceedings={Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bharath University, Chennai, India},
        publisher={EAI},
        proceedings_a={I3CAC},
        year={2021},
        month={6},
        keywords={system on chip (soc) electronic design automation (eda) sram (static random access memory) h-array generator network generator},
        doi={10.4108/eai.7-6-2021.2308775}
    }
    
  • Dr.A. Ranganayakulu
    Dr.V. Surya Narayana
    Dr.M.V. Nageswara Rao
    Year: 2021
    Design of SOC Based SRAM Cluster for Reliability and Functional Safety Applications
    I3CAC
    EAI
    DOI: 10.4108/eai.7-6-2021.2308775
Dr.A. Ranganayakulu1,*, Dr.V. Surya Narayana2, Dr.M.V. Nageswara Rao3
  • 1: Professor and HOD, Department of ECE, NRRIT, Guntur, A.P, India
  • 2: Professor and HOD, Department of CSE, RCEE, Eluru, A.P, India
  • 3: Professor and HOD, Department of ECE, GMRIT, Rajam, A.P, India
*Contact email: ranganayak2005@gmail.com

Abstract

In this paper the design of SOC based SRAM cluster is implemented for reliability and functional safety. The main objective of this research is to improve the accuracy and reduce the delay using SOC based design. The designed system initially generates the network using network generator. This network generator basically uses the strategies of both user’s clusterization and hierarchy optimization. After the strategy of hierarchy structure the electronic design automation (EDA) generator will generate the test standards based on the access of tests. This generated components test will be extracted based on the standards. Next H-Array generator will generate the arrays of H-arrays for different cluster level sub networks. All these arrays will be cross compiled by mapping the cells. At last this will be saved in SRAM cluster. Hence the SOC based SRAM cluster will improve the accuracy and reduce the delay in effective way.