Research Article
A Novel Watchdog Timer for Real-Time Intensive Applications
@INPROCEEDINGS{10.4108/eai.7-6-2021.2308611, author={Dr.R. SenthamilSelvan and Dr.V. Mahalakshmi and Dr.S.P. Vijayaragavan and Dr.S Arulselvi and Dr. M. Jasmin}, title={A Novel Watchdog Timer for Real-Time Intensive Applications}, proceedings={Proceedings of the First International Conference on Computing, Communication and Control System, I3CAC 2021, 7-8 June 2021, Bharath University, Chennai, India}, publisher={EAI}, proceedings_a={I3CAC}, year={2021}, month={6}, keywords={fpga watch dog timer (wdt) hardware description language (hdl) input and output interface verilog and vhdl}, doi={10.4108/eai.7-6-2021.2308611} }- Dr.R. SenthamilSelvan
Dr.V. Mahalakshmi
Dr.S.P. Vijayaragavan
Dr.S Arulselvi
Dr. M. Jasmin
Year: 2021
A Novel Watchdog Timer for Real-Time Intensive Applications
I3CAC
EAI
DOI: 10.4108/eai.7-6-2021.2308611
Abstract
Integrated systems utilized in security-critical applications require the very best accuracy. Externic monitoring watches are utilized in that structure naturally manages to get over failures associated with operating time. Most vacant exterior watch watches use extra circuits are regulate rest interlude and supply just partial appearance in terms of the performance. A document explains planning, style of enhanced arrangement of watchdog timer which utilized in security-demanding use. Various errors finding method are constructing watchdog, adding to its strength. A process is fairly common and not to observe procedure of a few relative method. This enables a planning is simply tailored to diverse use as dropping common price of a system. The efficiency of planned surveillance device to notice error is initially deliberate by examine the simulation outcome.
