cs 19(16): e1

Research Article

Battery life optimization techniques for ultra-low power SOCs

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  • @ARTICLE{10.4108/eai.5-11-2019.162591,
        author={Shweta Aladakatti and Shubham Singh and Jasdeep Jain},
        title={Battery life optimization techniques for ultra-low power SOCs},
        journal={EAI Endorsed Transactions on Cloud Systems},
        volume={5},
        number={16},
        publisher={EAI},
        journal_a={CS},
        year={2019},
        month={11},
        keywords={KPI (Key Power Indicators), SoC (System On Chip), Ultra Low Power (ULP), Battery Life (BL), Double Data Rate bandwidth (DDR BW), On Chip Variations (OCV), Mobile Industry Processor Interface (MIPI), embedded Display Port (eDP), Panel Self Refresh-2 (PSR2), High Bit Rate (HBR), Low Power (LP), Dynamic Random Access Memory (DRAM)},
        doi={10.4108/eai.5-11-2019.162591}
    }
    
  • Shweta Aladakatti
    Shubham Singh
    Jasdeep Jain
    Year: 2019
    Battery life optimization techniques for ultra-low power SOCs
    CS
    EAI
    DOI: 10.4108/eai.5-11-2019.162591
Shweta Aladakatti1,2,*, Shubham Singh1,2, Jasdeep Jain1,2
  • 1: SOC Power Design Engineer, Intel Technologies India pvt ltd
  • 2: Intel Technologies, SRR3 Bangalore, India
*Contact email: shweta.aladakatti@intel.com

Abstract

The urge for devices with longer battery life in today’s compute world has motivated multiple changes in the design, architecture, and SW optimizations. Ultra-Low Power products [Mobiles, Tablets, Notebooks, and Convertibles] are constrained by 2 major factors – thermal dissipation and supply of battery power. Thermal dissipation restricts power consumption of application processor, which additionally limits computational performance. Battery usage time is determined by power consumption of the device. Due to these reasons, power management to improve efficiency of electric power usage becomes a very crucial part of ULP products. Battery life suite is introduced with real time use cases or KPI’s to analyze battery life of the product. This paper presents the optimizations that were developed for improving the battery life performance of ULP SoCs. The use cases/KPI’s defined in BL suite were used as metrics to evaluate the features. We present the features in two categories spanning architecture and software optimization. A detailed power modeling exercise was undertaken for evaluating the features, including detailed model correlation with post-Si data from previous generation products. The combined benefit of the features translates to an overall improvement of ~34% SoC power and ~11.5% increase in battery life for suite i.e. ULP product is very close to the target of maintaining the hours of battery life expected by the suite. These features have been adopted by products across several segments.