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Proceedings of the 4th International Conference on Information Technology, Civil Innovation, Science, and Management, ICITSM 2025, 28-29 April 2025, Tiruchengode, Tamil Nadu, India, Part II

Research Article

Design and Implementation of a High-Performance Variable Latency Integer Divider in 15nm Technology

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  • @INPROCEEDINGS{10.4108/eai.28-4-2025.2358094,
        author={G.  Sujatha and Budda  Ahalya and Saladhi  Krupa and Varanasi  Meghana and Thoti  Kishan and B.  Abhisheek},
        title={Design and Implementation of a High-Performance Variable Latency Integer Divider in 15nm Technology},
        proceedings={Proceedings of the 4th International Conference on Information Technology, Civil Innovation, Science, and Management, ICITSM 2025, 28-29 April 2025, Tiruchengode, Tamil Nadu, India, Part II},
        publisher={EAI},
        proceedings_a={ICITSM PART II},
        year={2025},
        month={10},
        keywords={integer division variable latency low-power design 15nm technology cadence fpga asic},
        doi={10.4108/eai.28-4-2025.2358094}
    }
    
  • G. Sujatha
    Budda Ahalya
    Saladhi Krupa
    Varanasi Meghana
    Thoti Kishan
    B. Abhisheek
    Year: 2025
    Design and Implementation of a High-Performance Variable Latency Integer Divider in 15nm Technology
    ICITSM PART II
    EAI
    DOI: 10.4108/eai.28-4-2025.2358094
G. Sujatha1,*, Budda Ahalya1, Saladhi Krupa1, Varanasi Meghana1, Thoti Kishan1, B. Abhisheek1
  • 1: Sri Venkateswara College of Engineering
*Contact email: sujatha.g@svcolleges.edu.in

Abstract

Integer division is a fundamental operation in computer arithmetic, widely used in applications such as digital signal processing, cryptography, and artificial intelligence. However, due to its inherently sequential nature, integer division often becomes a performance bottleneck in modern computing systems. This paper presents a novel variable latency integer division algorithm, implemented and synthesized in 15nm technology using Cadence software. The proposed design dynamically skips unnecessary iterations by exploiting the relationship between the number of leading zeros in the divisor and the partial remainder, significantly reducing average latency and power consumption. Our implementation achieves an average latency of 1.45 clock cycles per 32-bit division, outperforming existing state-of-the-art designs. The design is validated through extensive simulations and benchmark testing, demonstrating its suitability for low-power embedded systems and high-performance computing applications.

Keywords
integer division, variable latency, low-power design, 15nm technology, cadence, fpga, asic
Published
2025-10-14
Publisher
EAI
http://dx.doi.org/10.4108/eai.28-4-2025.2358094
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