FPGA Implementation for Image Improved Edge Detection Algorithm Using Xilinx ISE Simulator

The Canny edge detection algorithm is one of the most widely used methods for edge detection due to its superior performance. However, it is a complex and timeconsuming process that also has a high hardware cost. In addition, most existing implementations use a fixed pair of high and low threshold values for all input images. Such fixed thresholds cannot automatically adapt to changes in the external detection environment, resulting in decreased performance. To address these issues, this paper proposes an improved Canny algorithm. It employs the Sobel operator and approximation methods to calculate the gradient magnitude and direction, thereby replacing complex operations and reducing hardware cost. Otsu’s algorithm is introduced to adaptively determine the image threshold. Since Otsu’s algorithm involves division operations that are slow and inefficient, this paper incorporates optimizations to improve efficiency. An optimized pipeline architecture is implemented for the Canny edge detection algorithm on an FPGA (Field Programmable Gate Array). The proposed method significantly enhances performance compared to the conventional approach, specifically on the FPGA device 7vx485tffg1157-3. The existing method, which used the conventional Canny algorithm with a pipeline architecture, achieved a delay of 6.061 ns (Maximum Frequency: 165.003 MHz) and consumed 1,908 Slice LUTs.