Research Article
Design and Analysis of Master Slave Flip Flop with Low Power, Reduced Delay and Area Efficiency
@INPROCEEDINGS{10.4108/eai.28-4-2025.2357800, author={T Shanti and S Abhishek Singh and D Chandu and K Bhanu Prakash}, title={Design and Analysis of Master Slave Flip Flop with Low Power, Reduced Delay and Area Efficiency}, proceedings={Proceedings of the 4th International Conference on Information Technology, Civil Innovation, Science, and Management, ICITSM 2025, 28-29 April 2025, Tiruchengode, Tamil Nadu, India, Part I}, publisher={EAI}, proceedings_a={ICITSM PART I}, year={2025}, month={10}, keywords={low-power design master-slave flip-flop clock gating dynamic power reduction sequential logic}, doi={10.4108/eai.28-4-2025.2357800} }- T Shanti
S Abhishek Singh
D Chandu
K Bhanu Prakash
Year: 2025
Design and Analysis of Master Slave Flip Flop with Low Power, Reduced Delay and Area Efficiency
ICITSM PART I
EAI
DOI: 10.4108/eai.28-4-2025.2357800
Abstract
This research introduces a power-efficient master-slave flip-flop utilizing clock gating techniques, designed and analyzed using Xilinx Vivado. The proposed approach minimizes dynamic power consumption by selectively deactivating the clock signal when the flip-flop is idle. Clock gating is utilized in Verilog HDL implementation, to avoid unnecessary transitions. The simulation results show a significant reduction in dynamic power (0.001 W) and better-worst negative slack (WNS) of 0.237 ns. With the use of only two slice registers and two slice LUTs this design maintains a good timing performance preserving optimal resource usage. These results demonstrate the efficiency of clock gating in power reduction for FPGA-based sequential logic circuits.
