A Three Stage Comparator and It’s Modified Version With High Speed and Low Kickback Noise

This work presents a comparative analysis of an existing and a proposed comparator circuit. The proposed circuit introduces additional transistors in the input stage, offering potential improvements in common-mode control, threshold adjustment, or gain. The fundamental operation of both circuits relies on a clocked regenerative latch to perform voltage comparisons. Simulation results, obtained using Micro wind, reveal a significant difference in power consumption between the two designs. The existing comparator exhibits a power consumption of 0.138 mW, while the proposed comparator demonstrates a substantially lower power consumption of 62.654 pW. This indicates that, under the specific simulation conditions, the proposed comparator achieves a power reduction of approximately 2.2 million times compared to the existing design. These findings suggest that the proposed modification offers a substantial advantage in terms of power efficiency, making it suitable for low-power applications. However, it is crucial to acknowledge that these power values are specific to the simulation setup, and a comprehensive evaluation across various operating conditions is necessary for a generalized comparison.