Research Article
FPGA Design and Optimization Implementation of GPS Positioning Algorithm
@INPROCEEDINGS{10.4108/eai.27-8-2020.2295315, author={Wei He and Zhi Jiang and Zengshan Tian and Mu Zhou and Shuai Lu}, title={FPGA Design and Optimization Implementation of GPS Positioning Algorithm}, proceedings={Proceedings of the 13th EAI International Conference on Mobile Multimedia Communications, Mobimedia 2020, 27-28 August 2020, Cyberspace}, publisher={EAI}, proceedings_a={MOBIMEDIA}, year={2020}, month={11}, keywords={field programmable gate array; parallel data processing; pipeline}, doi={10.4108/eai.27-8-2020.2295315} }- Wei He
Zhi Jiang
Zengshan Tian
Mu Zhou
Shuai Lu
Year: 2020
FPGA Design and Optimization Implementation of GPS Positioning Algorithm
MOBIMEDIA
EAI
DOI: 10.4108/eai.27-8-2020.2295315
Abstract
Propose a parallel data processing framework method based on field programmable gate array (FPGA). In this paper, the complexity analysis of GPS classic localization algorithm is carried out. Within the scope allowed by hardware logic resources, the FPGA hardware implementation framework is designed with the idea of area exchange rate, that is, a large number of pipeline operations are used in Verilog language programming to improve system processing speed. The experimental results show that FPGA achieves highprecision positioning, in the WGS-84 coordinate system, the error of the X-axis about 5m, and the error of the Y-axis and the Z-axis is about 2m.
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