Mismatch Analysis and Calibration Techniques in Modern CMOS: From Current Mirror to SAR ADC

This paper systematically reviews the mismatch response framework from underlying physical principles to upper-level system architecture. The study first analyzes the mismatch mechanism based on the Pelgrom model, then explores the impact of threshold voltage mismatch in the current mirror on the output current, and the mismatch problem between the capacitor array and the dynamic comparator in SAR ADC. The paper focuses on reviewing the evolution of calibration techniques, including chopper stabilization, dynamic component matching, digital pre-distortion, noise shaping, and the latest machine learning-assisted calibration technologies. Research shows that the design approach of co-designing digital algorithms and circuits can more effectively suppress mismatch compared to traditional pure circuit design, offering significant advantages in cost and flexibility. However, it still faces challenges in terms of increased circuit complexity in the analog domain and computational resource consumption in the digital domain.