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Proceedings of the 3rd International Conference on Mechanics, Electronics Engineering and Automation, ICMEEA 2026, April 24-26, 2026, Singapore, Singapore

Research Article

Analysis of Performance-Influencing Factors and Optimization Strategies for Single-Stage Amplifiers

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  • @INPROCEEDINGS{10.4108/eai.24-4-2026.2364984,
        author={Songyuan  He},
        title={Analysis of Performance-Influencing Factors and Optimization Strategies for Single-Stage Amplifiers},
        proceedings={Proceedings of the 3rd International Conference on Mechanics, Electronics Engineering and Automation, ICMEEA 2026, April 24-26, 2026, Singapore, Singapore},
        publisher={EAI},
        proceedings_a={ICMEEA},
        year={2026},
        month={9},
        keywords={Effect Parasitic Capacitance Optimization Strategies},
        doi={10.4108/eai.24-4-2026.2364984}
    }
    
  • Songyuan He
    Year: 2026
    Analysis of Performance-Influencing Factors and Optimization Strategies for Single-Stage Amplifiers
    ICMEEA
    EAI
    DOI: 10.4108/eai.24-4-2026.2364984
Songyuan He1,*
  • 1: Maynooth International Engineering College, Fuzhou University, Fuzhou, 350108, China
*Contact email: SONGYUAN.HE.2025@mumail.ie

Abstract

When semiconductor technology scales down steadily, single-stage amplifiers have significant difficulties in optimizing performance because of short-channel effects and parasitic parameters. This paper thoroughly looks into the important physical mechanisms constraining amplifier gain, with a focus on channel length modulation (CLM), the body effect, and the Miller effect. The study first finds out the theoretical effect of these factors on voltage gain, linearity, and bandwidth. To overcome these limitations, advanced device architectures like Gate-All-Around (GAA) and Fully Depleted SiliconOn-Insulator (FD-SOI) are studied, using their better electrostatic control to suppress CLM and the body effect. Precisely, a Cascode structure making use of active feedback (transistor T2) is proposed to remove the Miller effect. The research reveals that the combination of advanced process nodes and optimized circuit topologies is crucial for getting high gain and high bandwidth performance in modern analog integrated circuits.

Keywords
Effect, Parasitic Capacitance, Optimization Strategies
Published
2026-09-02
Publisher
EAI
http://dx.doi.org/10.4108/eai.24-4-2026.2364984
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