Research Article
Common-Mode Voltage Suppression of a Five-Level ANPC Inverter Based on a Novel SVPWM Strategy
@INPROCEEDINGS{10.4108/eai.24-4-2026.2364976, author={Sizhe Wei}, title={Common-Mode Voltage Suppression of a Five-Level ANPC Inverter Based on a Novel SVPWM Strategy}, proceedings={Proceedings of the 3rd International Conference on Mechanics, Electronics Engineering and Automation, ICMEEA 2026, April 24-26, 2026, Singapore, Singapore}, publisher={EAI}, proceedings_a={ICMEEA}, year={2026}, month={9}, keywords={five-level ANPC inverter novel SVPWM strategy CMV suppression capacitor-voltage balancing redundant switching states}, doi={10.4108/eai.24-4-2026.2364976} }- Sizhe Wei
Year: 2026
Common-Mode Voltage Suppression of a Five-Level ANPC Inverter Based on a Novel SVPWM Strategy
ICMEEA
EAI
DOI: 10.4108/eai.24-4-2026.2364976
Abstract
To address the issue that the amplitude of common-mode voltage (CMV) in inverters tends to increase as the number of voltage levels rises, this paper takes a three-phase five-level ANPC inverter as the study object and reviews a CMV suppression method based on a novel SVPWM strategy that reconstructs the space-vector diagram by selecting 19 vectors that generate zero CMV from the 125 space vectors of conventional five-level SVPWM, thereby suppressing CMV while substantially reducing the computational burden. Theoretical analysis and simulation results both demonstrate that the method can significantly reduce the CMV amplitude while maintaining output waveform quality and effectively balance capacitor-voltage; however, its linear modulation range is reduced compared with that of conventional SVPWM.
