From Logical Effort to Machine Learning: A Survey on Delay Modeling in Digital Circuits

As the process nodes of integrated circuits approach the nanoscale, precise delay modeling has become a key factor in determining the performance and reliability of chips. Traditional model-based methods have limitations. In contrast, the modeling paradigm based on machine learning has significant advantages. However, the two approaches have different fundamental ideas. This paper takes the technological development process of digital circuit delay modeling as an example, reviews the development history and comparison of the classic logic effort theory and machine learning techniques, and constructs a framework to analyze the differences between these two types of modeling methods from aspects such as modeling philosophy, accuracy and efficiency, interpretability, data dependence, and generalization ability. It is found that the two modeling ideas are not in a replacement relationship but complement each other. The traditional formula-driven method has high interpretability and is an effective method for simulation and design of core devices at the current stage; while the data-driven modeling method can obtain more accurate results by learning from large-scale data. From a practical perspective, the trend of big data and high computing power is unstoppable. Therefore, as the two continue to integrate, it will further promote development. Eventually, it will drive EDA towards a more intelligent "AI-native" direction.