Intelligent Adaptive VDD Scaling Architecture under the Breakthrough of Physical Limits

As Moore's Law continues to advance, integrated circuit process nodes continue to shrink. Power consumption and energy efficiency have become the primary bottlenecks restricting the improvement of chip performance. Power supply voltage (VDD) scaling is one of the core technologies for reducing chip power consumption and optimizing energy efficiency. Its applications always face a fundamental trade-off between performance delay and energy consumption. This article systematically reviews the evolution of VDD Scaling and Delay-Energy optimization techniques. It is divided into three key stages. First, the physical basis of the technology and its early theoretical construction are explained. Then, the core optimization methods in the era of process scaling are analyzed. Finally, the latest development trends in the post-Moore era will be discussed. By tracing the technological developments and key breakthroughs, this article provides researchers in related fields with a clear development framework and a well-defined road map for future research. It also provides theoretical reference and technical guidance for the design of next-generation high-efficiency integrated circuits