Research Article
Implementation of NoC on FPGA with Area and Power Optimization
@ARTICLE{10.4108/eai.23-5-2019.158953, author={Momil Ijaz and Huma Urooj and Muhammad Athar Javed Sethi}, title={Implementation of NoC on FPGA with Area and Power Optimization}, journal={EAI Endorsed Transactions on Context-aware Systems and Applications}, volume={6}, number={16}, publisher={EAI}, journal_a={CASA}, year={2019}, month={3}, keywords={Network on chip, node, switching, packet, crossbar}, doi={10.4108/eai.23-5-2019.158953} }- Momil Ijaz
Huma Urooj
Muhammad Athar Javed Sethi
Year: 2019
Implementation of NoC on FPGA with Area and Power Optimization
CASA
EAI
DOI: 10.4108/eai.23-5-2019.158953
Abstract
On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems, size, speed, power and area. The goal of working was to design a usable and researchable general-purpose 2x2 mesh NoC architecture, which is not application specific, and have optimized area and power. Desired NoC was coded and deployed on FPGA Spartan-3 kit in a generic mode, with the efficient area and power utilization than traditional deployments.
Copyright © 2019 Momil Ijaz et al., licensed to EAI. This is an open access article distributed under the terms of the Creative Commons Attribution licence (http://creativecommons.org/licenses/by/3.0/), which permits unlimited use, distribution and reproduction in any medium so long as the original work is properly cited.
