Research Article
Review of Network on Chip Routing Algorithms
@ARTICLE{10.4108/eai.23-12-2020.167793, author={Khurshid Ahmad and Muhammad Athar Javed Sethi}, title={Review of Network on Chip Routing Algorithms}, journal={EAI Endorsed Transactions on Context-aware Systems and Applications}, volume={7}, number={22}, publisher={EAI}, journal_a={CASA}, year={2020}, month={12}, keywords={System on Chip, Network on Chip, Routing Algorithm}, doi={10.4108/eai.23-12-2020.167793} }
- Khurshid Ahmad
Muhammad Athar Javed Sethi
Year: 2020
Review of Network on Chip Routing Algorithms
CASA
EAI
DOI: 10.4108/eai.23-12-2020.167793
Abstract
System on chip (SoC) is an integrated circuit in which components are communicating through the bus interconnection system. Network on chip (NoC) is a communication network for a multiprocessor system on chip (MPSoC). In NoC architecture node/ component of MPSOC are communicating through a network. The performance of NoC architecture depends on topology, routing algorithm and switching technique. In this paper, different NoC routing algorithms are review using basic parameters of NoC architecture and also provide some information about these parameters. It is concluded that most of the researchers are interested in design of the NoC routing algorithm, which efficiently transmits data from source to destination. When the routing algorithm is congestion aware, fault-tolerant, deadlock-free and live-lock free, then the latency of algorithm decreases and throughput increases.
Copyright © 2020 Khurshid Ahmad et al., licensed to EAI. This is an open access article distributed under the terms of the Creative Commons Attribution license, which permits unlimited use, distribution and reproduction in any medium so long as the original work is properly cited.