5th International ICST Conference on Communications and Networking in China

Research Article

A block-based parallel decoding architecture for convolutional codes

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  • @INPROCEEDINGS{10.4108/chinacom.2010.77,
        author={Chengyi Su and Yu Zhang and Changyong Pan and Xiaofeng Wan},
        title={A block-based parallel decoding architecture for convolutional codes},
        proceedings={5th International ICST Conference on Communications and Networking in China},
        publisher={IEEE},
        proceedings_a={CHINACOM},
        year={2011},
        month={1},
        keywords={Convolutional Codes Parallel Decoding Viterbi algorithm FPGA},
        doi={10.4108/chinacom.2010.77}
    }
    
  • Chengyi Su
    Yu Zhang
    Changyong Pan
    Xiaofeng Wan
    Year: 2011
    A block-based parallel decoding architecture for convolutional codes
    CHINACOM
    ICST
    DOI: 10.4108/chinacom.2010.77
Chengyi Su1, Yu Zhang1,*, Changyong Pan1, Xiaofeng Wan1
  • 1: State Key Laboratory on Microwave and Digital Communications, Tsinghua National Laboratory for Information Science and Technology, Department of Electronic Engineering, Tsinghua University, Beijing, China
*Contact email: zhang-yu@mail.tsinghua.edu.cn

Abstract

This paper delivers a block-based parallel convolutional decoding architecture in which several Viterbi decoders work concurrently to decode consecutive code blocks. Each code block contains a preamble and a postamble which are duplicate data from neighbor blocks. Preamble and postamble are beneficial to the continuity and correctness of decoding output. Simulation results demonstrate that this architecture has a negligible coding-gain loss, compared with the conventional Viterbi decoder. An FPGA implementation of this architecture achieves a throughput up to 1.2 Gbps.