Instruction Set Simulator Generation Using HARMLESS, a New Hardware Architecture Description Language

Instruction set simulators are commonly used in embedded system development processes for early functional validation of code and exploration of new instruction set design. Such a simulator can be either hand-written or generated automatically, based on a Hardware Architecture Description Language. Automatically generated simulators are more maintainable and are faster to develop, but they also generally suffer from low performances in simulation speed and a lack of expressivity in the description. This paper introduces HARMLESS, a new language to automatically generate instruction set simulators. It differs from other languages in many ways: it resolves most expressivity issues and naturally offers a exible description by explicitly splitting the syntax (mnemonic), format (binary code) and behavior descriptions. Thus, it allows an incremental description, starting for example by the disassembler (requiring format and syntax descriptions). When the frst two descriptions are validated, the behavior description is added to obtain the simulator. Some results are also presented on the simulator build process, especially on the decoder generation. An instruction cache is also introduced to speed up simulation in the same order of magnitude as hand-written simulators. Some experimental results are eventually presented.