Research Article
A methodology and a case-study for Network-on-Chip based MP-SoC architectures
@INPROCEEDINGS{10.4108/ICST.NANONET2007.2122, author={Sergio V. Tota and Mario R. Casu and Paolo Motto and Massimo Ruo Roch and Maurizio Zamboni}, title={A methodology and a case-study for Network-on-Chip based MP-SoC architectures}, proceedings={2nd Internationa ICST Conference on Nano-Networks}, proceedings_a={NANO-NET}, year={2010}, month={5}, keywords={NoC MPSoC}, doi={10.4108/ICST.NANONET2007.2122} }- Sergio V. Tota
Mario R. Casu
Paolo Motto
Massimo Ruo Roch
Maurizio Zamboni
Year: 2010
A methodology and a case-study for Network-on-Chip based MP-SoC architectures
NANO-NET
ICST
DOI: 10.4108/ICST.NANONET2007.2122
Abstract
The many-core design paradigm requires flexible and modular hardware and software components to provide the required scalability of next-generation on-chip multiprocessor architectures. A multidisciplinary approach is necessary to consider all the interactions between the different components of the design. In this work a complete design methodology is proposed, tackling at once the aspects of hardware architecture, programming model and design automation. The proposed design flow has been used in the implementation of a multiprocessor Network-on-Chip based system, the NoCRay graphic accelerator. The system uses 8 Tensilica LX processors and has been physically implemented on a Xilinx Virtex-4 LX-160 FPGA reporting a 17.3M equivalent gate-count. Performance are compared with a commercial general purpose processor and show good results considering the low frequency of the prototype.