Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs

This paper presents a model order reduction technique using subspace iterative scheme for high speed coupled integrated circuit interconnects in nanometer designs. The salient feature of this technique is less complexity in computation of a few smallest poles of the reduced order model. This paper shows that the subspace iterative scheme produces reduced systems that accurately follow the time- and frequency- domain responses of the original system. Experimental results show that the subspace iterative scheme achieves more accuracy than the variational Krylov-subspace-based model order reduction techniques. Significant reduction in computational expense is achieved as the size of the reduced equations is much less than that of the original system.