Research Article
Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs
@INPROCEEDINGS{10.4108/ICST.NANONET2007.2084, author={J.V.R. Ravindra and M.B. Srinivas}, title={Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs}, proceedings={2nd Internationa ICST Conference on Nano-Networks}, proceedings_a={NANO-NET}, year={2010}, month={5}, keywords={Model Order Reduction Interconnects Krylov-subspace}, doi={10.4108/ICST.NANONET2007.2084} }- J.V.R. Ravindra
M.B. Srinivas
Year: 2010
Generating Reduced Order Models using Subspace Iteration for Linear RLC Circuits in Nanometer Designs
NANO-NET
ICST
DOI: 10.4108/ICST.NANONET2007.2084
Abstract
This paper presents a model order reduction technique using subspace iterative scheme for high speed coupled integrated circuit interconnects in nanometer designs. The salient feature of this technique is less complexity in computation of a few smallest poles of the reduced order model. This paper shows that the subspace iterative scheme produces reduced systems that accurately follow the time- and frequency- domain responses of the original system. Experimental results show that the subspace iterative scheme achieves more accuracy than the variational Krylov-subspace-based model order reduction techniques. Significant reduction in computational expense is achieved as the size of the reduced equations is much less than that of the original system.
