1st International ICST Conference on Nano-Networks

Research Article

3D Nanowire-Based Programmable Logic

  • @INPROCEEDINGS{10.1109/NANONET.2006.346223,
        author={B.  Gojman and R. Rubin and C.  Pilotto and A. DeHon and T.  Tanamoto},
        title={3D Nanowire-Based Programmable Logic},
        proceedings={1st International ICST Conference on Nano-Networks},
  • B. Gojman
    R. Rubin
    C. Pilotto
    A. DeHon
    T. Tanamoto
    Year: 2007
    3D Nanowire-Based Programmable Logic
    DOI: 10.1109/NANONET.2006.346223
B. Gojman1, R. Rubin1, C. Pilotto1, A. DeHon1, T. Tanamoto1
  • 1: Dept. of CS, California Inst. of Technol., Pasadena, CA


In nanowire-based logic, the semiconducting material (e.g., Si, GaN, SiGe) is grown into individual nanowires rather than being part of the substrate. This offers us the opportunity to stack multiple layers of nanowires to create a three-dimensional logic structure which has high quality semiconductors in all vertical layers. The authors detail a feasible three-dimensional programmable logic architecture which can plausibly be realized from layers of semiconducting nanowires, making only modest assumptions about the control and placement of individual nanowires in the assembly. This shows a natural path for continuing to scale areal logic density once nanowire pitches approach fundamental limits. The authors show that the three dimensional systems are volumetrically efficient, with the surface area reducing roughly in proportion to the number of vertical layers. The authors further show that, on average, delay is reduced 18% from compact layout in three dimensions. For only a 20% area impact, the authors show how to avoid adding any manufacturing steps to physically isolate portions of nanowire layers