Skew Insensitive Physical Links for Network on Chip

D.  Mangano; R.  Locatelli; A. Scandurra; C.   Pistritto; M.  Coppola; L. Fanucci; F.  Vitullo; D.  Zandri

1st International ICST Conference on Nano-Networks

Research Article

Skew Insensitive Physical Links for Network on Chip

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/NANONET.2006.346236,
    author={D.  Mangano and R.  Locatelli and A. Scandurra and C.   Pistritto and M.  Coppola and L. Fanucci and F.  Vitullo and D.  Zandri},
    title={Skew Insensitive Physical Links for Network on Chip},
    proceedings={1st International ICST Conference on Nano-Networks},
    publisher={IEEE},
    proceedings_a={NANO-NET},
    year={2007},
    month={4},
    keywords={},
    doi={10.1109/NANONET.2006.346236}
}

D. Mangano
R. Locatelli
A. Scandurra
C. Pistritto
M. Coppola
L. Fanucci
F. Vitullo
D. Zandri
Year: 2007
Skew Insensitive Physical Links for Network on Chip
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346236

D. Mangano¹, R. Locatelli¹, A. Scandurra¹, C. Pistritto¹, M. Coppola¹, L. Fanucci¹, F. Vitullo¹, D. Zandri¹

1: HPC - On Chip Commun. Syst., STMicroelectron.

Abstract

The increasing complexity, in terms of both physical dimension and performance demand of current systems on chip (SoCs) led to the development of new suitable interconnect architecture, leveraging on computer network technology, called network on chip (NoC). This paper describes two architectures of advanced physical link for NoC, the former based on mesochronous technology, the latter based on asynchronous

Published: 2007-04-16
Publisher: IEEE

: http://dx.doi.org/10.1109/NANONET.2006.346236