Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices

A.  Venkataratnam; A.K.  Goel

1st International ICST Conference on Nano-Networks

Research Article

Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices

Cite: BibTeX Plain Text

@INPROCEEDINGS{10.1109/NANONET.2006.346218,
    author={A.  Venkataratnam and A.K.  Goel},
    title={Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices},
    proceedings={1st International ICST Conference on Nano-Networks},
    publisher={IEEE},
    proceedings_a={NANO-NET},
    year={2007},
    month={4},
    keywords={},
    doi={10.1109/NANONET.2006.346218}
}

A. Venkataratnam
A.K. Goel
Year: 2007
Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices
NANO-NET
IEEE
DOI: 10.1109/NANONET.2006.346218

A. Venkataratnam¹, A.K. Goel¹

1: Dept. of Electr. & Comput. Eng., Michigan Technol. Univ., Houghton, MI

Abstract

Single electron transistor is a nanoelectronic three terminal device. It provides current conduction characteristics comparable to a MOSFET. In this paper, the authors have designed and simulated logic circuit architectures with a combination of SET and conventional devices such as MOSFETs and comparators. The performances of these hybrid architectures and their advantages and disadvantages with SET standalone circuits have also been studied

Published: 2007-04-16
Publisher: IEEE

: http://dx.doi.org/10.1109/NANONET.2006.346218