Area and Power Modeling Methodologies for Networks-on-Chip

Networks-on-chip (NoCs) are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well-established CAD deployment tools to tackle the large amount or available degrees of freedom, starting from the choice of a network topology. "Silicon-aware" optimization tools are now emerging in literature; they select a NoC topology taking into account the tradeoff between performance and hardware cost, i.e. area and power consumption. A key requirement for the effectiveness of these tools, however, is the availability of accurate analytical models for power and area. Such models are unfortunately not as available and well understood as those for traditional communication fabrics. In this work, given a NoC reference architecture, the authors present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose two strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. The models are parameterized on several architectural, synthesis-related and traffic variables, resulting in maximum flexibility. The authors finally assess the accuracy of the models