9th International Conference on Cognitive Radio Oriented Wireless Networks

Research Article

An Adaptive Detector Implementation for MIMO-OFDM Downlink

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  • @INPROCEEDINGS{10.4108/icst.crowncom.2014.255419,
        author={Shahriar Shahabuddin and Janne Janhunen and Essi Suikkanen and Heidi Steendam and Markku Juntti},
        title={An Adaptive Detector Implementation for MIMO-OFDM Downlink},
        proceedings={9th International Conference on Cognitive Radio Oriented Wireless Networks},
        publisher={IEEE},
        proceedings_a={CROWNCOM},
        year={2014},
        month={7},
        keywords={cognitive mimo tta detector},
        doi={10.4108/icst.crowncom.2014.255419}
    }
    
  • Shahriar Shahabuddin
    Janne Janhunen
    Essi Suikkanen
    Heidi Steendam
    Markku Juntti
    Year: 2014
    An Adaptive Detector Implementation for MIMO-OFDM Downlink
    CROWNCOM
    IEEE
    DOI: 10.4108/icst.crowncom.2014.255419
Shahriar Shahabuddin1,*, Janne Janhunen1, Essi Suikkanen1, Heidi Steendam2, Markku Juntti1
  • 1: Centre for Wireless Communications, University of Oulu
  • 2: Digcom research group, TELIN department, Ghent University, Belgium
*Contact email: sshahabu@ee.oulu.fi

Abstract

Cognitive radio (CR) systems require flexible and adaptive implementations of signal processing algorithms. An adaptive symbol detector is needed in the baseband receiver chain to achieve the desired flexibility of a CR system. This paper presents a novel design of an adaptive detector as an application-specific instruction-set processor (ASIP). The ASIP template is based on transport triggered architecture (TTA). The processor architecture is designed in such a manner that it can be programmed to support different suboptimal multiple-input multiple-output (MIMO) detection algorithms in a single TTA processor. The linear minimum mean-square error (LMMSE) and three variants of the selective spanning for fast enumeration (SSFE) detection algorithms are considered. The detection algorithm can be switched between the LMMSE and SSFE according to the bit error rate (BER) performance requirement in the TTA processor. The design can be scaled for different antenna configurations and different modulations. Some of the algorithm architecture co-optimization techniques used here are also presented. Unlike most other detector ASIPs, high level language is used to program the processor to meet the timeto- market requirements. The adaptive detector delivers 4.88 - 49.48 Mbps throughput at a clock frequency of 200 MHz on 90 nm technology.