8th International Conference on Cognitive Radio Oriented Wireless Networks

Research Article

Design of a TV White Space Converter Prototype Towards Cognitive Radio for WLAN Routers

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  • @INPROCEEDINGS{10.4108/icst.crowncom.2013.252073,
        author={Iyappan Subbiah and Moritz Schrey and Arun Ashok and Gabor Varga and Andreas Achtzehn and Marina Petrova and Stefan Heinen},
        title={Design of a TV White Space Converter Prototype Towards Cognitive Radio for WLAN Routers},
        proceedings={8th International Conference on Cognitive Radio Oriented Wireless Networks},
        publisher={ICST},
        proceedings_a={CROWNCOM},
        year={2013},
        month={11},
        keywords={cognitive radio whitespace 80211 frontend},
        doi={10.4108/icst.crowncom.2013.252073}
    }
    
  • Iyappan Subbiah
    Moritz Schrey
    Arun Ashok
    Gabor Varga
    Andreas Achtzehn
    Marina Petrova
    Stefan Heinen
    Year: 2013
    Design of a TV White Space Converter Prototype Towards Cognitive Radio for WLAN Routers
    CROWNCOM
    IEEE
    DOI: 10.4108/icst.crowncom.2013.252073
Iyappan Subbiah1,*, Moritz Schrey1, Arun Ashok1, Gabor Varga1, Andreas Achtzehn2, Marina Petrova2, Stefan Heinen1
  • 1: Chair of Integrated Analog Circuits and RF Systems
  • 2: Institute for Networked Systems
*Contact email: isubbiah@ias.rwth-aachen.de

Abstract

We report on the development of a frequency converter frontend that enables 2.4 GHz IEEE 802.11 WLAN devices to operate in unused parts of the UHF spectrum, the so-called TV whitespaces. The new frontend features separate TX and RX paths with automatic directionality switching and in-hardware energy detection. Equipped with a standard antenna port at the input side, and a fully configurable transmit chain controlled through a user-accessible microcontroller, this whitespace converter (WSC) with commercial off-the-shelf components is particularly suitable for cognitive radio (CR) research. We discuss the specific challenges in the design of a WSC for 802.11 WLAN routers. The complete architecture is presented, and preliminary performance results from a level plan optimization are discussed.