Research Article
FPGA Based Implementation of Overlapped QC-LDPC Decoder with Limited Resources
@INPROCEEDINGS{10.4108/icst.chinacom.2014.256381, author={Xu jia and Bie xia and Zheng Jian and Lei yang}, title={FPGA Based Implementation of Overlapped QC-LDPC Decoder with Limited Resources}, proceedings={9th International Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2015}, month={1}, keywords={overlapped message passing; latency; fpga; qc-ldpc decoder}, doi={10.4108/icst.chinacom.2014.256381} }- Xu jia
Bie xia
Zheng Jian
Lei yang
Year: 2015
FPGA Based Implementation of Overlapped QC-LDPC Decoder with Limited Resources
CHINACOM
IEEE
DOI: 10.4108/icst.chinacom.2014.256381
Abstract
In this paper, we propose a simplified architecture based on overlapped message passing (OMP) for QC-LDPC decoders with Normalized Minimum Sum (NMS) algorithm, aiming to reduce decoding latency with as less additional resources as possible. According to the OMP architecture, the two stages of NMS, namely check node process and variable node process, could be overlapped. Hence, overall decoding latency is reduced and hardware utilization efficiency (HUE) is improved. Based on the proposed OMP architecture, two irregular QC-LDPC decoders are implemented in serial and partly-parallel styles in FPGA respectively. Experimental results show that, achieving the same decoding performance, the serial QC-LDPC decoder with proposed OMP architecture can reduce latency by 39.1% compared with that of the decoder with TPMP(Two Stages Message Passing) architecture, and the latency reduction of partly-parallel decoder varies with degrees of parallelism.
