Research Article
Architecture and Implementation of a Vector MAC Unit for Complex Number
@INPROCEEDINGS{10.4108/icst.chinacom.2014.256357, author={Yuan Luo and Zhifeng Zhang and Xinlin Huang and Jun Wu and Xin Chen}, title={Architecture and Implementation of a Vector MAC Unit for Complex Number}, proceedings={9th International Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2015}, month={1}, keywords={signal processing dsp simd vector unsigned/signed complex multiply-accumulate unit}, doi={10.4108/icst.chinacom.2014.256357} }- Yuan Luo
Zhifeng Zhang
Xinlin Huang
Jun Wu
Xin Chen
Year: 2015
Architecture and Implementation of a Vector MAC Unit for Complex Number
CHINACOM
IEEE
DOI: 10.4108/icst.chinacom.2014.256357
Abstract
Signal processing requires high performance digital signal processors(DSP) and hardware accelerators. Real and complex multiply-accumulate(MAC) units are the most critical computation units in the DSPs and accelerators, which great- ly impact the performance, power and chip area of the sig- nal processing system. A fixed-point Single-Instruction-Multiple- Data(SIMD)/vector MAC architecture is presented in this paper. It supports 8-bit/16-bit/32-bit real and complex MAC operations. The proposed vector MAC unit can be fully pipelined. Compared to normal real MAC unit, the proposed vector MAC unit needs to double the resources. For the computation of real and imaginary parts, the operand muxing and extra carry-save adders(CSA) are all required to ensure a correct result. The "shared segmentation" and "shared subtree" methods can be applied to share the circuit among 8-bit, 16-bit and 32-bit operations.