Research Article
Design and Performance Evaluation of Data Flow Processor
@INPROCEEDINGS{10.4108/icst.chinacom.2014.256245, author={Wenjun Su}, title={Design and Performance Evaluation of Data Flow Processor}, proceedings={9th International Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2015}, month={1}, keywords={data driven data flow self-timed pipeline computer architecture}, doi={10.4108/icst.chinacom.2014.256245} }- Wenjun Su
Year: 2015
Design and Performance Evaluation of Data Flow Processor
CHINACOM
IEEE
DOI: 10.4108/icst.chinacom.2014.256245
Abstract
Traditional control flow computer has some disadvantages, such as high power consumption, poor performance of parallel computing, clock skew problem, the worst performance, unnatural programming language, and so on. For this case, we design a data flow processor (DFP). DFP adopts self-timed pipeline that is different from normal asynchronous pipeline. The self-timed pipeline employed in the DFP uses a four-phase communication protocol, with bounded-delay data transmission. Throughput is changeable in self-timed pipeline and signal in different stage can be delayed different time. The sequence of the operation in data flow computer is depended on relationship between operands and validity of operands, and it is not fixed by programmers. DFP can overcome the shortcomings of traditional control-flow processor, and more in line with people's thinking habits. For FFT, the performance of data flow processor is about three times of the performance of the DSP.
