An Efficient Fault Tolerant Routing Interconnect System for Neural NOC

Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. Regarding intra-chip communication, this recommend crossbar arbitrage placement, virtual interrupt and path-based parallelization strategies for virtual channel routing, leading to higher NoC output with lower hardware costs. For multicast-based traffic. Regarding inter-chip communication, this propose a lightweight NoC compatible chip-to-chip interconnection scheme to allow efficient interconnection for NoC-based NN chips. In addition, this will test the proposed methods with four Field Programmable Gate Arrays (FPGAs) on four hardwired Deep Neural Network (DNN) chips. The experimental results show that the proposed interconnection network can effectively handle data traffic with high thr