Research Article
ITFComp: A Compression Algorithm for ARM Architecture Instruction Trace Files
@INPROCEEDINGS{10.4108/eai.24-8-2015.2260596, author={Mohammad Qasem and Lukas Pustina}, title={ITFComp: A Compression Algorithm for ARM Architecture Instruction Trace Files}, proceedings={Eighth EAI International Conference on Simulation Tools and Techniques}, publisher={ACM}, proceedings_a={SIMUTOOLS}, year={2015}, month={8}, keywords={performance instruction trace files compression memory addresses hardware simulation arm architecture}, doi={10.4108/eai.24-8-2015.2260596} }- Mohammad Qasem
Lukas Pustina
Year: 2015
ITFComp: A Compression Algorithm for ARM Architecture Instruction Trace Files
SIMUTOOLS
ICST
DOI: 10.4108/eai.24-8-2015.2260596
Abstract
Testing the performance of a new computational component is costly due to the need of prototyping different setups. Therefore, trace driven hardware simulations are used. Instruction Trace Files (ITFs) are files containing traces of executed instructions in a program's run and are used as an input for hardware simulations. ITFs tend to be large in size, causing a storage challenge. Many trace reduction techniques exist to deal with the ITFs' storage challenge. In this paper we introduce ITFComp, a compression algorithm that combines general purpose compression methods with knowledge about ARM architecture ITFs' structure to reduce their size. ITFComp also works on compressing data memory addresses accessed by instructions within ITFs to further reduce an ITF size. Results show a reduction of 600 times on average when combined with LZMA compression algorithm. This reduction is 4 times better than when using LZMA alone, and 10 times better than when using DEFLATE. ITFComp introduces a negligible overhead in the decompression time (less than 1%).
