Design of a Multi-mode Clock Divider Based on Dual Finite State Machine

Modern System-on-Chip (SoC) devices drive various modules that require clock signals with different frequencies and duty cycles. Still, existing digital clock dividers often lack flexibility in complex mode switching and precise duty cycle control. To meet the requirement, this study proposes a multi-mode clock divider based on a three-stage dual-channel Finite State Machine (FSM). The design uses 3-bit binary coding for selecting the target frequency division ratio and 2-bit coding for choosing the specific duty cycle adjustments. Moreover, this paper adopts a right-shift algorithm to calculate the thresholds efficiently. In even division cases, the system employs a single rising-edge FSM to save power, while the system uses dual-channel FSMs and logical “OR” operation to achieve half-cycle precision in odd division conditions. Verified by ModelSim simulation with a 100MHz input clock and 8500ns duration, the divider managed to output desired frequencies, with both odd and even divisions showing little duty cycle deviation, despite some malfunctions in specific situations. This reliable design provides a solution for SoC clock management, supporting dynamic frequency scaling and low-power strategies, and offers a practical reference for sequential logic-based timing control.