cs 19(15): e5

Research Article

Layout Automation Techniques to Optimize Time-to-Market Factor

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  • @ARTICLE{10.4108/eai.16-7-2019.162216,
        author={G S Aishwarya Meghana and Sheetal Y Kochrekar and Poornima Venkatasubramanian},
        title={Layout Automation Techniques to Optimize Time-to-Market Factor},
        journal={EAI Endorsed Transactions on Cloud Systems},
        volume={5},
        number={15},
        publisher={EAI},
        journal_a={CS},
        year={2019},
        month={7},
        keywords={Automation, Layout, Time to Market, IP, Sensors, IoT, Mobiles},
        doi={10.4108/eai.16-7-2019.162216}
    }
    
  • G S Aishwarya Meghana
    Sheetal Y Kochrekar
    Poornima Venkatasubramanian
    Year: 2019
    Layout Automation Techniques to Optimize Time-to-Market Factor
    CS
    EAI
    DOI: 10.4108/eai.16-7-2019.162216
G S Aishwarya Meghana1, Sheetal Y Kochrekar1, Poornima Venkatasubramanian1,*
  • 1: Design Enablement (DE), Samsung Semiconductor India Research (SSIR), Bangalore, India
*Contact email: p.venkatasub@samsung.com

Abstract

With the ever growing demand for IPs in the domain of mobiles, 5G, and sensors for wearables and IoT applications, time to market becomes a crucial factor. There is always a need for delivering IPs to the competitive market in very less time without compromising on the quality. This necessitates the development of a reliable automation technique that can be easily integrated into the design cycle and Quality assurance flow of an IP. In this paper, we propose a generic automation flow for generating seed layouts for any technology node. The proposed flow reduces manual efforts and improves overall productivity.