Research Article
Design and Implementation of DMA Transfers in WISHBONE interface
@INPROCEEDINGS{10.4108/eai.15-8-2015.2260781, author={Lei Lei and Jun Wu and Tong Sun and Songlin Cheng and Xin Chen}, title={Design and Implementation of DMA Transfers in WISHBONE interface}, proceedings={10th EAI International Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2015}, month={9}, keywords={dsp wishbone dma synchronization of asynchronous clock asic}, doi={10.4108/eai.15-8-2015.2260781} }- Lei Lei
Jun Wu
Tong Sun
Songlin Cheng
Xin Chen
Year: 2015
Design and Implementation of DMA Transfers in WISHBONE interface
CHINACOM
IEEE
DOI: 10.4108/eai.15-8-2015.2260781
Abstract
The Digital Signal Processor (DSP) is a specialized microprocessor, with its architecture optimized for the operational needs of digital signal processing.It often uses special memory architectures that are able to fetch multiple data and/or instructions at the same time.With applying to WISHBONE bus interface it is much easier to connect the cores, and therefore much easier to create a custom System on Chip (SOC) such as the DSP.In order to increase the data transaction from DSP core to WISHBONE Slave module, this paper proposes a special Direct Memery Access (DMA) which supports a three-ports interface of data transaction. This DMA also offers burst mode and the address list mode of data transaction which can speed the data transmission and make it more flexible. In the process of the design and implement, a synchronization of asynchronous clock issue needs to be solved. The final implementations have been done in ASIC. The functionality of the design is synthesized using Design Compiler and placement and routing by IC compiler.
