Research Article
Design and Implementation of a Memory Architecture in DSP for wireless communication
@INPROCEEDINGS{10.4108/eai.15-8-2015.2260780, author={Chaoxing Zhao and Jun Wu and Xin Chen}, title={Design and Implementation of a Memory Architecture in DSP for wireless communication}, proceedings={10th EAI International Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2015}, month={9}, keywords={dsp vliw simd memory architecture computer architecture asic}, doi={10.4108/eai.15-8-2015.2260780} }- Chaoxing Zhao
Jun Wu
Xin Chen
Year: 2015
Design and Implementation of a Memory Architecture in DSP for wireless communication
CHINACOM
IEEE
DOI: 10.4108/eai.15-8-2015.2260780
Abstract
Digital signal processors (DSP) play an important role in signal processing, wireless communication and many other fields. With the improvement of DSP's computing performance, memory architecture became the neck of the whole DSP's efficiency. A new memory architecture which can be accessed by two computation slots, DMA controller, debug module and wishbone bus in parallel is presented in this paper. Our data memory capacity is 1MB and instruction memory capacity is 256KB. After synthesized, placed, and routed in a commercial 65nm low power process, the area of our data memory is about 8, 600, 600$\upmu$$m^2$, and the area of our instruction memory is about 2, 140, 000$\upmu$$m^2$. The delay result of our data memory is 1.65ns (SS), and the delay result of our instruction memory is 1.78ns (SS).