Research Article
A Design of FPGA-based DSRC Receiver
@INPROCEEDINGS{10.4108/eai.15-8-2015.2260612, author={Xiang Li and Fen Liu and Chao Wang and Fuqiang Liu and Changwei He and Chenghao Lv and Wei Yin and Qingquan Zou}, title={A Design of FPGA-based DSRC Receiver}, proceedings={10th EAI International Conference on Communications and Networking in China}, publisher={IEEE}, proceedings_a={CHINACOM}, year={2015}, month={9}, keywords={dedicated short range communications (dsrc) ad hoc network test-bed wireless transceiver}, doi={10.4108/eai.15-8-2015.2260612} }- Xiang Li
Fen Liu
Chao Wang
Fuqiang Liu
Changwei He
Chenghao Lv
Wei Yin
Qingquan Zou
Year: 2015
A Design of FPGA-based DSRC Receiver
CHINACOM
IEEE
DOI: 10.4108/eai.15-8-2015.2260612
Abstract
The Dedicated Short Range Communications (DSRC)-based vehicular communications suffer from highly dynamic outdoor environments, which cannot be characterized correctly and accurately by computer-based simulations. Evaluating new algorithms and schemes in real outdoor environments highlights the need for an easy-to-use DSRC test-bed. In this paper, a DSRC receiver is designed and implemented by using the Field Programmable Gate Array (FPGA) platform. Several related transceiver algorithms for the signal detection, frame synchronization and channel estimation are reviewed and analyzed by combining the IEEE 802.11p standard with the vehicular communication environments, and a set of proper algorithms are adopted to enhance the system performance. The implementation of the proposed receiver is further optimized according to the characteristics of FPGA. The implementation result agrees that a significant reduction on the hardware resource usage is achieved by the proposed design.