cs 19(14): e5

Research Article

Methodology for validating Nest Memory Management Unit

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  • @ARTICLE{10.4108/eai.15-3-2019.162139,
        author={Nandhini  Rajaiah and Jayakumar N Sankarannair and Larry S  Leitner},
        title={Methodology for validating Nest Memory Management Unit},
        journal={EAI Endorsed Transactions on Cloud Systems},
        volume={5},
        number={14},
        publisher={EAI},
        journal_a={CS},
        year={2019},
        month={3},
        keywords={Post-silicon validation, address translation mechanisms, microprocessor, accelerator, design verification},
        doi={10.4108/eai.15-3-2019.162139}
    }
    
  • Nandhini Rajaiah
    Jayakumar N Sankarannair
    Larry S Leitner
    Year: 2019
    Methodology for validating Nest Memory Management Unit
    CS
    EAI
    DOI: 10.4108/eai.15-3-2019.162139
Nandhini Rajaiah1,*, Jayakumar N Sankarannair1, Larry S Leitner2
  • 1: IBM, Bangalore, India
  • 2: IBM, Austin, United States
*Contact email: nrajaiah@in.ibm.com

Abstract

The growing demand for performance makes the processor logic design more complex, thereby making post-silicon validation a critical and complex step in processor development life cycle. There are complex units with newer timing and control logic paths which are almost impossible to exercise in regular verification environments. One such unit to cater to newer workloads in recent superscalar processors is the Nest Memory Management Unit (NMMU), a memory management unit for all I/O devices. This paper presents some of the major challenges in validating Nest MMU. A postsilicon validation framework is proposed to mitigate these challenges. An asynchronous non-blocking accelerator job submission model is used in this approach to increase the translation traffic from the agent to NMMU. Core MMU translation is used as the reference model to validate nest MMU. The processor core storage exception handlers are leveraged to minimize the validation tool software development effort and to increase the efficiency of validation as well. This method makes use of an optimized threshold-based checker to detect potential NMMU hardware issues. The proposed methodology has been experimentally evaluated in Power9 NMMU to demonstrate the effectiveness of the method in providing considerable stress to the unit.